1. Field of the Invention
This invention relates to a decimal multiplication mechanism for fixed and floating point mechanism of a computer and particularly to a system and method of multiplication without resulting leading zero detection (LZD) using the decimal multiplication mechanism.
2. Description of Background
Before our invention we developed a system for IBM for performing multiplication on decimal data including input registers for inputting a multiplier and a multiplicand. The multiplier included one or more digits. The system also included one or more two cycle adders and mechanism. The mechanism received the multiplier and the multiplicand into the input registers. With this mechanism, a running sum then is reset to zero. The mechanism also performs for each of the digits in the multiplier in order from least significant digit to most significant digit: creating a partial product of the digit and the multiplicand; and adding the partial product to the running sum using the two cycle adders. When the loop is completed for each of the digits in the multiplier, the mechanism outputs the running sum as the result. This process however must build in hardware support to account for the fact that a multiplication of a multiplier of N digits in length by a multiplicand of M digits in length yields a product of either M+N or M+N−1 digits in length. Because of this, they must post process the infinitely precise result and select the appropriate value for the final product. Such mechanisms often maintain unnecessary least significant digits which will be truncated in the final result. They also require additional hardware such as leading zero detection circuits to accurately determine the final number of significant digits in the product. Such an example of this approach is U.S. Pat. No. 7,519,647 issued Apr. 14, 2009, entitled “System and Method for Providing a Decimal Multiply Algorithm Using a Double Adder” naming Carlough et. al. inventors and assigned to IBM. This U.S. Pat. No. 7,519,647 including its accompanying drawings is fully incorporated herein by reference.